Ad converter

ABSTRACT

A successive approximation type AD converter includes: a comparator comparing an analog input signal and a DA-converted comparison code; and a control circuit. When an output of the comparator settles before a limit time period has passed since the comparator started a comparison operation, the control circuit updates the comparison code on the basis of the settled output of the comparator. When the limit time period has passed before the output of the comparator settles, the control circuit updates the comparison code not on the basis of the present output of the comparator.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Continuation Application of U.S. Ser. No.14/435,940 filed Apr. 15, 2015, which is the U.S. National Phase ofPCT/JP2012/076811 filed Oct. 17, 2012. The subject matter of each isincorporated herein by reference in entirety.

TECHNICAL FIELD

The present invention relates to an AD (Analog-to-Digital) converter,and is suitably used for an asynchronous successive approximation typeAD converter, for example.

BACKGROUND ART

A successive approximation type AD converter typically serves to convertan analog input signal into a binary digital value by a binary searchmethod. The successive approximation type AD converter is classifiedroughly into a synchronous type and an asynchronous type.

In the synchronous AD converter, a sampling clock used for determining asampling period are generated based on the externally supplied clock anda timing clock used for controlling the operation of a comparator. TheAD converter operates in synchronization with these clocks. Since thesynchronous AD converter requires a circuit for generating these clocksand also requires wiring lines for clocks to extend therein, theconsumption current becomes relatively large and the circuit isincreased in area.

The asynchronous AD converter serves to start the comparison operationin the next cycle based on the signal showing that a comparisonoperation has been completed, and thus, does not require supply of aclock signal in a constant cycle. Accordingly, the power consumption andthe area can be reduced as compared with the case of the synchronous ADconverter (for example, see “A 6-bit 600-MS/s 5.3-mW Asynchronous ADC in0.13-μm CMOS” by Chen, et. al., IEEE Journal of Solid-State Circuits,Vol. 41, December in 2006, pages 2669 to 2680 (Non-Patent Document 1)).

According to the asynchronous-type AD converter, however, as theabsolute value of the potential difference between the input analogsignal and the reference signal becomes smaller, the time until theoutput signal of the comparator settles becomes longer. In the casewhere the absolute value of the potential difference between bothsignals is extremely small, the required number of comparison for one ADconversion cannot be carried out to the end, thereby leading to anextremely large AD conversion error.

Japanese Patent Laying-Open No. 2010-45579 (PTD 1) discloses acomparison circuit configured to shorten a determination time period.Specifically, when comparing an input signal and a reference signal, thecomparison circuit in this document generates the first comparison valuelarger than the reference signal by a predetermined value and the secondcomparison value smaller than the reference signal by the predeterminedvalue. The comparison circuit includes: the first comparator generatingthe first determination signal in accordance with the result obtained bycomparing the input signal and the first comparison value; and thesecond comparator generating the second determination signal inaccordance with the result obtained by comparing the input signal andthe second comparison value. The comparison circuit further includes anoutput selection circuit: detecting one of the first determinationsignal and the second determination signal that is first generated; andselecting the first generated signal to output the selected signal as adetermination signal.

CITATION LIST Patent Document

PTD 1: Japanese Patent Laying-Open No. 2010-45579

Non Patent Document

NPD 1: S. M. Chen and R. W. Brodersen, “A 6-bit 600-MS/s 5.3-mWAsynchronous ADC in 0.13-μm CMOS”, IEEE Journal of Solid-State Circuits,Vol. 41, December in 2006, pages 2669 to 2680.

SUMMARY OF INVENTION Technical Problem

According to the successive approximation type AD converter including acomparison circuit disclosed in the above-mentioned Japanese PatentLaying-Open No. 2010-45579 (PTD 1), a reference signal is obtained by DA(Digital-to-Analog)-converting a comparison code generated in asuccessive approximation register. The first comparison value and thesecond comparison value mentioned above are generated by adding apositive/negative predetermined analog voltage to this analog referencesignal. Accordingly, the first and second comparison values are toinclude errors associated with addition of an analog voltage, whichleads to a problem that the final AD conversion error becomes relativelylarge. If two DA converters are provided for generating the first andsecond comparison values, addition of an analog voltage becomesunnecessary, which however causes an increase in the circuit area.

Other problems and novel features will become apparent from thedescription of the present specification and the accompanying drawings.

Solution to Problem

A successive approximation type AD converter according to one embodimentincludes: a comparator comparing an analog input signal and aDA-converted comparison code; and a control circuit. When an output ofthe comparator settles before a limit time period has passed since thecomparator started a comparison operation, the control circuit updatesthe comparison code on the basis of the settled output of thecomparator. When the limit time period has passed before the output ofthe comparator settles, the control circuit updates the comparison codenot on the basis of a present output of the comparator.

Advantageous Effects of Invention

According to the AD converter in one embodiment described above, evenwhen the absolute value of the input potential difference of thecomparator becomes extremely small, an AD conversion value with arelatively small error can be obtained within a desired period of time.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram schematically showing one example of theentire configuration of a semiconductor device including an AD converteraccording to the first embodiment.

FIG. 2 is a block diagram showing the configuration of the AD converterin FIG. 1.

FIG. 3 is a circuit diagram showing one example of the configuration ofeach of a comparator and an SR latch circuit in FIG. 2.

FIG. 4 is a diagram schematically showing one example of a signalwaveform of each part in the AD converter in FIG. 2.

FIG. 5 is a diagram for illustrating the conversion operation by the ADconverter in the first embodiment.

FIG. 6 is a diagram showing the configuration of a part of the ADconverter according to the second embodiment.

FIG. 7 is a diagram for illustrating the operation of a limit timedetermination circuit in FIG. 6.

FIG. 8 is a diagram showing one example of the detailed configuration ofa delay circuit in FIG. 6.

FIG. 9 is a diagram showing the configuration of a part of an ADconverter according to the third embodiment.

FIG. 10 is a diagram showing the configuration of a part of an ADconverter according to the fourth embodiment.

FIG. 11 is a diagram showing the configuration of a part of an ADconverter according to the fifth embodiment.

DESCRIPTION OF EMBODIMENTS

Each embodiment will be hereinafter described in detail with referenceto the accompanying drawings, in which the same or correspondingcomponents are designated by the same reference characters, anddescription thereof will not be repeated.

First Embodiment Configuration Example of Semiconductor Device

FIG. 1 is a block diagram schematically showing one example of theentire configuration of a semiconductor device including an AD converteraccording to the first embodiment.

Referring to FIG. 1, a semiconductor device 1 includes a micro controlunit (MCU) 2, a successive approximation type AD converter 10, a clockgenerator 3, other peripheral circuits 4, a power supply circuit that isnot shown, and the like. MCU 2 includes a CPU (Central Processing Unit)core, a memory, a timer, an input/output interface, and the like. ADconverter 10 and other peripheral circuits 4 are connected to MCU 2 andcontrolled by this MCU 2. Clock generator 3 generates a clock used as areference of the operation of semiconductor device 1, and supplies theclock to each unit.

Configuration of AD Converter

FIG. 2 is a block diagram showing the configuration of the AD converterin FIG. 1. Referring to FIG. 2, AD converter 10 is an asynchronoussuccessive approximation type AD converter. AD converter 10 includes aDA converter (DAC: Digital-to-Analog Converter) 14, a comparator 11provided with a latch circuit, an SR (Set-Reset) latch circuit 12, and acontrol circuit 13.

1. DA Converter 14

DA converter 14 serves to DA-convert a comparison code CC output fromcontrol circuit 13. DA converter 14 generates a differential signalDACOUT (a positive phase signal DACOUTP and a negative phase signalDACOUTN) showing the potential difference between a sampled analog inputsignal VIN (a positive phase signal VINP and a negative phase signalVINN) and DA-converted comparison code CC, and outputs the generateddifferential signal DACOUT to comparator 11.

DA converter 14 may be configured as a capacity DAC, as a combination ofa capacity main DAC and a resistance sub DAC, or as a resistance DAC.

2. Comparator and SR Latch Circuit 2.1 Outline

Comparator 11 is implemented by adding the function of a latch circuitto a complete differential amplifier having a differential input and adifferential output. Comparator 11 receives differential signal DACOUT(positive phase signal DACOUTP and negative phase signal DACOUTN) outputfrom DA converter 14. In accordance with the value of differential inputsignal DACOUT, comparator 11 generates and outputs a differential signalLATCHOUT so as to cause one of positive phase signal LATCHOUTP andnegative phase signal LATCHOUTN to attain an H level (high level) and tocause the other of these positive and negative phase signals to attainan L level (low level). Differential output signal LATCHOUT is held inSR latch circuit 12 and output to control circuit 13.

As another option, sampled input signal VIN and DA-converted comparisoncode CC each may be input into comparator 11 as a single-ended signal,and comparator 11 may be configured to output differential signalLATCHOUT in accordance with the potential difference between both of theinput single-ended signals.

A clock signal CLKCOMP is further input into comparator 11. When clocksignal CLKCOMP is asserted, comparator 11 starts a comparison operation.When clock signal CLKCOMP is negated, comparator 11 is reset. In thefirst embodiment, clock signal CLKCOMP is defined as an H active signal,in which clock signal CLKCOMP is asserted at the H level and negated atthe L level. Needless to say, clock signal CLKCOMP may be defined as anL active signal.

In the first embodiment, positive phase signal LATCHOUTP and negativephase signal LATCHOUTN output from reset comparator 11 each are at an Hlevel. When clock signal CLKCOMP is asserted, one of positive phasesignal LATCHOUTP and negative phase signal LATCHOUTN changes into an Llevel in accordance with the value of differential input signal DACOUT.

2.2 Detailed Example of Circuit Configuration

FIG. 3 is a circuit diagram showing one example of the configuration ofeach of the comparator and the SR latch circuit in FIG. 2. Referring toFIG. 3, comparator 11 includes PMOS (Positive-channel Metal OxideSemiconductor) transistors MP0 to MPS, and NMOS (Negative-channel MetalOxide Semiconductor) transistors MN0 to MN3 and MN6.

PMOS transistor MP0 and NMOS transistors MN2 and MN0 are connected inthis order in series between a power supply node VDD and a node ND4.PMOS transistor MP1 and NMOS transistors MN3 and MN1 are connected inthis order in series between power supply node VDD and node ND4, andalso connected in parallel with transistors MP0, MN2 and MN0 that areconnected in series. NMOS transistors MN0 and MN1, which form adifferential pair, have gates receiving output signals DACOUTP andDACOUTN, respectively, from DA converter 14 in FIG. 2. PMOS transistorMP0 and NMOS transistor MN2 each have a gate connected to a connectionnode ND1 between PMOS transistor MP1 and NMOS transistor MN3 (anon-inversion output node of comparator 11). PMOS transistor MP1 andNMOS transistor MN3 each have a gate connected to a connection node ND0between PMOS transistor MP0 and NMOS transistor MN2 (an inversion outputnode of comparator 11). Thereby, transistors MP0, MP1, MN2, and MN3 forma latch circuit. Positive phase signal LATCHOUTP is output fromconnection node ND1 (the non-inversion output node of comparator 11),and negative phase signal LATCHOUTN is output from connection node ND0(the inversion output node of comparator 11).

An NMOS transistor MN6 is connected between node ND4 and a ground nodeVSS. NMOS transistor MN6 has a gate into which clock signal CLKCOMP isinput. When clock signal CLKCOMP is at an L level, NMOS transistor MN6is turned off. When clock signal CLKCOMP is at an H level, NMOStransistor MN6 is turned on and functions as a constant current source.

PMOS transistor MP2 is connected between power supply node VDD andconnection node ND0 while PMOS transistor MP3 is connected between powersupply node VDD and connection node ND1. PMOS transistor MP4 isconnected between power supply node VDD and a connection node ND2 ofNMOS transistors NM2 and MN0. PMOS transistor MP5 is connected betweenpower supply node VDD and a connection node ND3 of NMOS transistors MN3and MN1. These PMOS transistors MP2 to MP5 each have a gate into whichclock signal CLKCOMP is input. When clock signal CLKCOMP is at an Hlevel, PMOS transistors MP2 to MP5 are brought into an OFF state(comparator 11 is in an operating state). When clock signal CLKCOMP isat an L level, PMOS transistors MP2 to MP5 are brought into an ON state(comparator 11 is in a reset state), in which case output nodes ND1 andND0 of comparator 11 are fixed at an H level.

SR latch circuit 12 includes: inverters INV1 and INV2 receiving outputsignals LATCHOUTP and LATCHOUTN, respectively, of comparator 11; and NORgates NR1 and NR2. NOR gate NR1 outputs a signal obtained by invertingan OR operation result of the output signal of inverter INV1 and theoutput signal of NOR gate NR2. NOR gate NR2 outputs a signal obtained byinverting an OR operation result of the output signal of inverter INV2and the output signal of NOR gate NR1. The output signal of NOR gate NR2is output to control circuit 13 as an output signal COMPOUT of the SRlatch circuit.

When clock signal CLKCOMP is negated, that is, when output signalsLATCHOUTP and LATCHOUTN of comparator 11 each are at an H level, theinternal state of SR latch circuit 12 does not change and the logiclevel of output signal COMPOUT does not change. When clock signalCLKCOMP is asserted, comparator 11 outputs differential signal LATCHOUTaccording to differential input signal DACOUTP to SR latch circuit 12.When input positive phase signal DACOUTP of comparator 11 is larger thaninput negative phase signal DACOUTN, output positive phase signalLATCHOUTP is maintained at an H level while output negative phase signalLATCHOUTN changes into an L level. At this time, output signal COMPOUTof SR latch circuit 12 attains an L level. When input positive phasesignal DACOUTP of comparator 11 is smaller than input negative phasesignal DACOUTN, output positive phase signal LATCHOUTP changes into an Llevel while output negative phase signal LATCHOUTN is maintained at an Hlevel. At this time, output signal COMPOUT of SR latch circuit 12attains an H level.

2.3 Modification of FIG. 3

In comparator 11 in FIG. 3, power supply node VDD and ground node VSSmay be replaced with each other, each PMOS transistor may be replacedwith an NMOS transistor, and each NMOS transistor may be replaced with aPMOS transistor. In this case, SR latch circuit 12 is formed only of NORgates NR1 and NR2 without including inverters INV1 and INV2.

In the case of the above-described configuration, comparator 11 receivesa signal obtained by inverting the logic level of clock signal CLKCOMP.When clock signal CLKCOMP is negated, output signals LATCHOUTP andLATCHOUTN of comparator 11 each attain an L level. When clock signalCLKCOMP is asserted, in comparator 11, one of output signals LATCHOUTPand LATCHOUTN changes into an H level in accordance with differentialinput signal DACOUT. In response to this change of differential outputsignal LATCHOUT, the internal state of SR latch circuit 12 changes.

3. Control Circuit

Again referring to FIG. 2, control circuit 13 includes: a logic gate(NAND gate) 15 for determining whether the output of comparator 11 hassettled or not; a limit time determination circuit 16; a logic gate (ORgate) 17; a clock generation circuit 18; and a successive approximationcontrol circuit 20.

3.1 Logic Gate (NAND Gate) 15

Logic gate 15 serves as a 2-input NAND circuit that performs a NANDoperation for output signals LATCHOUTP and LATCHOUTN of comparator 11.When clock signal CLKCOMP is negated, output signals LATCHOUTP andLATCHOUTN of comparator 11 each are at an H level. Accordingly, anoutput signal Main_in of logic gate 15 attains an L level. When clocksignal CLKCOMP is asserted and one of NANDs of output signals LATCHOUTPand LATCHOUTN from comparator 11 changes into an L level (that is, whenthe output of comparator 11 settles), output signal Main_in of logicgate 15 changes into an H level. In the first embodiment, output signalMain_in of the logic gate is defined as H active.

In summary, logic gate 15 functions as a determination unit thatdetermines whether the output of comparator 11 has settled or not. Whenthe output of comparator 11 settles, output signal (determinationsignal) Main_in of logic gate 15 changes from an L level into an H level(asserted).

As another option, as described in the above 2.3, when output signalsLATCHOUTP and LATCHOUTN of comparator 11 in the reset state each are atan L level, logic gate 15 is formed, for example, by an OR gate.

3.2 Limit Time Determination Circuit

When a limit time period has passed since clock signal CLKCOMP wasasserted, a limit time determination circuit 16 changes an output signalSub_in from an L level into an H level (in the first embodiment, outputsignal Sub_in of limit time determination circuit 16 is defined as Hactive). In other words, limit time determination circuit 16 functionsas a determination unit that determines whether the limit time periodhas passed or not since clock signal CLKCOMP was asserted. When thelimit time period has passed, output signal (determination signal)Sub_in of limit time determination circuit 16 changes from an L levelinto an H level (asserted).

When clock signal CLKCOMP is negated, limit time determination circuit16 immediately sets output signal Sub_in back to an L level (negates) inorder not to exert an influence upon the operation of successiveapproximation control circuit 20.

3.3 Logic Gate (OR Gate) 17

When at least one of output signal Main_in of logic gate 15 and outputsignal Sub_in of limit time determination circuit 16 is asserted, logicgate (OR gate) 17 asserts an output signal VALID (in the firstembodiment, the VALID signal is defined as H active).

In general, as the absolute value of the potential difference betweensampled input signal VIN and DA-converted comparison code CC (that is,the input potential difference of comparator 11) becomes smaller, thetime until the output of comparator 11 settles becomes longer. Theabove-mentioned limit time period is set in order to avoid such asituation that AD conversion of all bits cannot be completed in the casewhere the absolute value of the input potential difference is extremelysmall. Even if the output of comparator 11 does not settle, the VALIDsignal is asserted when the limit time period has passed since clocksignal CLKCOMP was asserted (that is, since comparator 11 started acomparison operation). In response to this VALID signal, clockgeneration circuit 18 and successive approximation control circuit 20proceeds to the next cycle.

The limit time period is determined depending on the bit accuracy of ADconversion such that the required number of all comparison operationsare completed during a time period until the next sampling periodstarts. Alternatively, the limit time period may be determined so as toproceed to the next cycle in the case where the absolute value ofdifferential signal DACOUT input into comparator 11 is smaller than theabsolute value of the quantization error of the AD converter (±0.5×LSB;note LSB: Least Significant Bit).

3.4 Clock Generation Circuit

In response to negation of clock signal CLKIN showing a sampling period(in response to the change from an H level into an L level in the firstembodiment), clock generation circuit 18 asserts clock signal CLKCOMPthat is to be output to comparator 11 (changes the signal from an Llevel into an H level). Thereby, the first comparison operation bycomparator 11 is started. At this point of time, the VALID signal isnegated (being at an L level).

When a predetermined time period has passed since clock generationcircuit 18 detected that the VALID signal was asserted (changed from anL level into an H level), this clock generation circuit 18 negates clocksignal CLKCOMP (changes the signal into an L level). Thereby, comparator11 is changed into a reset state.

When a predetermined time period has passed since clock signal CLKCOMPwas negated, clock generation circuit 18 asserts clock signal CLKCOMP(changes the signal into an H level). Thereby, the comparison operationin the next cycle is started.

3.5 Successive Approximation Control Circuit

When detecting that the VALID signal has been asserted, successiveapproximation control circuit 20 updates comparison code CC based onoutput signal COMPOUT of SR latch circuit 12. In other words, in thecase where the output of comparator 11 settles before the limit timeperiod has passed, successive approximation control circuit 20 generatescomparison code CC used in the next cycle based on the comparison resultof comparator 11 after settlement stored in SR latch circuit 12. Whenthe limit time period has passed before the output of comparator 11settles, successive approximation control circuit 20 uses the previouscomparison result stored in SR latch circuit 12 as the presentcomparison result (that is, not based on the present output ofcomparator 11), to generate comparison code CC to be used in the nextcycle.

In addition, as described later with reference to FIG. 5, even in thecase where the limit time period has passed before the output ofcomparator 11 settles, the final AD conversion error results in about 1LSB if the limit time period is appropriately set.

As shown in FIG. 2, successive approximation control circuit 20 morespecifically includes a shift register 21, a bit register 22, a latchcircuit 23, and a delay circuit 24. The value of shift register 21 isupdated in response to the VALID signal. Each bit of shift register 21corresponds to a State signal. The State signal shows the information asto which number of cycles the comparison operation is being performed.The value of bit register 22 is updated based on output signal COMPOUTof SR latch circuit 12 for each cycle. The contents of bit register 22are output to DA converter 14 as comparison code CC and also stored inlatch circuit 23. When the time period determined by delay circuit 24has passed since the sampling period ended by fall of clock signalCLKIN, the digital value stored in latch circuit 23 is output as an ADconversion output.

Operation of AD Converter

FIG. 4 is a diagram schematically showing one example of a signalwaveform of each part of the AD converter in FIG. 2. FIG. 4 shows clocksignal CLKIN, clock signal CLKCOMP, output signal LATCHOUT of comparator11, output signal Main_in of logic gate 15, output signal Sub_in oflimit time determination circuit 16, VALID signal, and output signalCOMPOUT of SR latch circuit 12 in this order from the top. Althoughoutput signal COMPOUT is a 1-bit signal showing the value at an H levelor an L level, FIG. 4 shows the signal at an H level and the signal atan L level that are overlapped with each other. FIG. 4 also shows Statesignals corresponding to the first bit and the second bit of shiftregister 21, comparison code CC, and an output signal of DA converter14. Although not shown in FIG. 4, in fact, the output of DA converter 14changes in accordance with the value of comparison code CC. Referring toFIGS. 2 and 4, the operation of AD converter 10 will be hereinaftercollectively described.

Clock signal CLKIN attains an H level during the time period from timet1 to time t2. Differential input signals VINP and VINN are sampledduring this time period.

When clock signal CLKIN falls to an L level at time t2, output signalsDACOUTP and DACOUTN of DA converter 14 are input into comparator 11.Furthermore, in response to fall of clock signal CLKIN, clock generationcircuit 18 changes clock signal CLKCOMP into an H level (time t3). Whenclock signal CLKCOMP is changed into an H level, comparator 11 startsthe comparison operation in the first cycle.

At next time t4, one of positive phase signal LATCHOUTP and negativephase signal LATCHOUTN output from comparator 11 changes into an L level(that is, the output of comparator 11 settles). In response to thechange of output signal LATCHOUT of comparator 11, output signal Main_inof logic gate 15 changes into an H level, and further, the VALID signalchanges into an H level (time t5). In the first cycle, the timing atwhich the output of comparator 11 settles (time t4) is prior to time t6corresponding to the time at which a limit time period TP1 has passedsince clock signal CLKCOMP rose.

In response to rise of the VALID signal at time t5, the first Statesignal changes into an H level. Furthermore, in response to the changeof output signal LATCHOUT of comparator 11, output signal COMPOUT of SRlatch circuit 12 changes. Successive approximation control circuit 20updates comparison code CC based on output signal COMPOUT of SR latchcircuit 12.

When a predetermined time period TP2 has passed since time t5 at whichthe VALID signal changed into an H level, clock generation circuit 18changes the clock signal into an L level (time t7). Furthermore, when apredetermined time period TP3 has passed since clock signal CLKCOMP waschanged into an L level, clock generation circuit 18 changes clocksignal CLKCOMP into an H level (time t8). When clock signal CLKCOMP ischanged into an H level, comparator 11 starts the comparison operationin the next second cycle.

When limit time period TP1 has passed at next time t9 since clock signalCLKCOMP rose, output signal Sub_in of limit time determination circuit16 changes into an H level. Thereby, the VALID signal changes into an Hlevel (time t10). In the second cycle, the output of comparator 11settles at time t11 that is after time t9 at which limit time period TP1has passed.

In response to rise of the VALID signal at time t10, the second Statesignal changes into an H level. Although successive approximationcontrol circuit 20 updates comparison code CC in accordance with outputsignal COMPOUT of SR latch circuit 12, output signal COMPOUT of SR latchcircuit 12 is not changed at this point of time. In other words,successive approximation control circuit 20 updates comparison code CCusing the previous comparison result of comparator 11 as a presentcomparison result.

In the following, similarly, when predetermined time period TP2 haspassed since time t10 at which the VALID signal changed into an H level,clock generation circuit 18 changes the clock signal into an L level(time t12). When predetermined time period TP3 has passed since clocksignal CLKCOMP was changed into an L level, clock generation circuit 18changes clock signal CLKCOMP into an H level (time t13). When clocksignal CLKCOMP is changed into an H level, comparator 11 starts thecomparison operation in the next third cycle.

Specific Example of AD Conversion

FIG. 5 is a diagram for illustrating the conversion operation by the ADconverter in the first embodiment. FIG. 5 shows an example of 5-bit ADconversion by a binary search method. The value of input signal VIN isassumed to be 8.1 in decimal number. Referring to FIGS. 2 and 5, firstexplained will be the case where no limit time period is set for thecomparison operation.

In the first cycle, successive approximation control circuit 20 sets acomparison code at “10000”. As a result of comparison by comparator 11,the DA conversion value (16 in decimal number) of the comparison code islarger than the input signal (8.1). Accordingly, successiveapproximation control circuit 20 decides the value of the mostsignificant bit (MSB) at “0”, and sets the comparison code in the nextsecond cycle at “01000”.

In the second cycle, the DA conversion value (8 in decimal number) ofthe comparison code is smaller than the input signal (8.1). Accordingly,successive approximation control circuit 20 decides the value of thesecond bit at “1”, and sets the comparison code in the next third cycleat “01100”.

In the third cycle, the DA conversion value (12 in decimal number) ofthe comparison code is larger than the input signal (8.1). Accordingly,successive approximation control circuit 20 decides the value of thethird bit at “0”, and sets the comparison code in the next fourth cycleat “01010”.

In the fourth cycle, the DA conversion value (10 in decimal number) ofthe comparison code is larger than the input signal (8.1). Accordingly,successive approximation control circuit 20 decides the value of thefourth bit at “0”, and sets the comparison code in the next fifth cycleat “01001”.

In the fifth cycle, the DA conversion value (9 in decimal number) of thecomparison code is larger than the input signal (8.1). Accordingly,successive approximation control circuit 20 decides the value of theleast significant bit (LSB) at “0”, and decides the final AD conversionvalue at “01000”.

Then, the case where a limit time period is set for a comparisonoperation will be explained. Specifically, it is assumed that, in theabove-mentioned second cycle, the limit time period has passed beforethe output of comparator 11 settles, and output signal Sub_in of limittime determination circuit 16 in FIG. 2 was asserted. In this case,successive approximation control circuit 20 decides the value of thesecond bit at “0” that is the same value as the most significant bitthat is the bit before this second bit, and sets the comparison code inthe next third cycle at “00100”.

In the third cycle, the DA conversion value (4 in decimal number) of thecomparison code is smaller than the input signal (8.1). Accordingly,successive approximation control circuit 20 decides the value of thethird bit at “1”, and sets the comparison code in the next fourth cycleat “00110”.

In the fourth cycle, the DA conversion value (6 in decimal number) ofthe comparison code is smaller than the input signal (8.1). Accordingly,successive approximation control circuit 20 decides the value of thefourth bit at “1”, and sets the comparison code in the next fifth cycleat “00111”.

In the fifth cycle, the DA conversion value (7 in decimal number) of thecomparison code is smaller than the input signal (8.1). Accordingly,successive approximation control circuit 20 decides the value of theleast significant bit (LSB) at “1”, and decides the final AD conversionvalue at “00111”.

As described above, the difference of the AD conversion value betweenthe case where a limit time period is set for the comparison operationand no limit time period is set for the comparison operation is only 1LSB. If a comparison operation is further performed once or twice usingthe known redundant cycle technique, the AD conversion value can becorrectly determined up to the least significant bit.

In addition, when the limit time period has passed before the output ofcomparator 11 settles, the previous comparison result does notnecessarily have to be used as it is. In the above-described example, atthe time when the value of the second bit is decided at “0”, the finalAD conversion value is set at “00111”, and at the time when the value ofthe second bit is decided at “1”, the final AD conversion value is setat “01000”. Therefore, even if the value of the second bit is decided at“0” or “1”, the difference of the final AD conversion value results inonly 1 LSB.

Effects of the First Embodiment

According to the first embodiment, when the limit time period has passedsince comparator 11 started a comparison operation, AD converter 10operates so as to proceed to the next cycle even if the output ofcomparator 11 does not settle. As a result of this, even when theabsolute value of the difference of input voltage of comparator 11 in acertain cycle (or the value of the differential input signal) becomesextremely small, the AD conversion value with a relatively small errorcan be obtained within a desired time period.

Second Embodiment

FIG. 6 is a diagram showing the configuration of a part of the ADconverter according to the second embodiment. An AD converter 10Aaccording to the second embodiment has a configuration obtained by morespecifically modifying limit time determination circuit 16 in FIG. 2.Referring to FIG. 6, limit time determination circuit 16A includes adelay circuit 30 and a logic gate (AND gate) 31.

Delay circuit 30 delays the timing of each of rise and fall of clocksignal CLKCOMP. The delay time of delay circuit 30 corresponds to alimit time period TP1 described in the first embodiment. The delay timeof delay circuit 30 can be adjusted in accordance with the value of eachbit of register 29 provided in AD converter 10A. The contents ofregister 29 can be rewritten through MCU 2 in FIG. 1.

Logic gate (AND gate) 31 receives clock signal CLKCOMP and the outputsignal of delay circuit 30. When clock signal CLKCOMP is asserted (an Hlevel) and the output signal of delay circuit 30 is asserted (an Hlevel), output signal Sub_in of logic gate 31 is asserted (attains an Hlevel).

Since other configurations of AD converter 10A are the same as those inFIG. 2, description thereof will not be repeated. In FIG. 6, the samecomponents as those in FIG. 2 are designated by the same referencecharacters.

FIG. 7 is a diagram for illustrating the operation of the limit timedetermination circuit in FIG. 6. Referring to FIGS. 6 and 7, it isassumed that clock signal CLKCOMP changes into an H level at time t1,and clock signal CLKCOMP changes into an L level at time t3. The riseand fall of the output signal of delay circuit 30 are delayed till timet2 and time t4, respectively.

Output signal Sub_in of logic gate 31 is obtained by performing an ANDoperation for clock signal CLKCOMP and the output signal of delaycircuit 30. Therefore, output signal Sub_in of limit time determinationcircuit 16A is asserted at time t2 (changes into an H level) with adelay of the delay time of delay circuit 30 (corresponding to a limittime period) from the timing at which clock signal CLKCOMP is asserted(time t1). When clock signal CLKCOMP is negated at time t3, outputsignal Sub_in of limit time determination circuit 16A is negatedimmediately (changes into an L level). In other words, the sameoperation as that of limit time determination circuit 16 described withreference to FIG. 2 can be implemented.

FIG. 8 is a diagram showing one example of the detailed configuration ofa delay circuit in FIG. 6. Referring to FIG. 8, delay circuit 30includes a plurality of delay units DL1, DL2, . . . , and DLn connectedin series. Delay units DL1, DL2, and DLn correspond to bits of register29, respectively. Each delay unit has the same configuration, and thedelay time is controlled by the corresponding bit of register 29. FIG. 8representatively shows the configuration of delay unit DL1.

Delay unit DL1 includes inverters 40 to 43 connected in series, switchelements (for example, MOS transistors) 45 and 46, and an inverter 44.Switch element 45 is connected in series to inverters 40 to 43, andturned ON or OFF in accordance with the logical value (1 or 0) of thecorresponding bit of register 29. Switch element 46 is provided in apath by which inverters 40 to 43 are bypassed. Also, switch element 46is turned ON or OFF in accordance with the value obtained by inverter 44inverting the logical value of the corresponding bit of register 29.Therefore, the path passing through inverters 40 to 43 and the pathbypassing inverters 40 to 43 can be switched in accordance with thevalue of the corresponding bit of register 29.

According to AD converter 10A in the above-described second embodiment,as in the case of the first embodiment, an AD conversion value with arelatively small error can be obtained within a desired time period evenwhen the absolute value of the input potential difference of comparator11 (that is, the value of differential input signal DACOUT) in a certaincycle becomes extremely small. Limit time determination circuit 16A usedin AD converter 10A can be implemented by a relatively simple circuitconfiguration.

Third Embodiment

FIG. 9 is a diagram showing the configuration of a part of an ADconverter according to the third embodiment. An AD converter 10Baccording to the third embodiment has a configuration obtained by morespecifically modifying limit time determination circuit 16 in FIG. 2.Referring to FIG. 9, limit time determination circuit 16B includes adelay circuit 30 and a D latch circuit 32.

Delay circuit 30 delays the timing of each of rise and fall of clocksignal CLKCOMP. The configuration of delay circuit 30 is the same asthat having been described with reference to FIG. 8. The delay time ofdelay circuit 30 can be adjusted in accordance with each bit value ofregister 29 provided in AD converter 10B. The contents of register 29are rewritten through MCU 2 in FIG. 1.

Clock signal CLKCOMP is input into an input terminal D and an inversionreset terminal /R of D latch circuit 32 while the output signal of delaycircuit 30 is input into clock terminal CK. Output signal Sub_in oflimit time determination circuit 16B is output from an output terminal Qof D latch circuit 32.

According to the configuration of the above-described limit timedetermination circuit 16B, at the point of time when the delay time ofdelay circuit 30 (corresponding to a limit time period) has passed sinceclock signal CLKCOMP rose to an H level, clock signal CLKCOMP at an Hlevel is output from output terminal Q as an output signal Sub_in. Atthe falling edge of clock signal CLKCOMP, the signal of an L level isinput into inversion reset terminal /R, so that output signal Sub_in ofan L level is immediately output. In other words, the same operation asin limit time determination circuit 16 having been described withreference to FIG. 2 can be implemented.

Since other configurations of AD converter 10B are the same as those inFIG. 2, description thereof will not be repeated. In FIG. 9, the samecomponents as those in FIG. 2 are designated by the same referencecharacters.

According to AD converter 10B in the third embodiment described above,as in the first embodiment, an AD conversion value with a relativelysmall error can be obtained within a desired time period even when theabsolute value of the input potential difference of comparator 11 in acertain cycle (that is, a value of the differential input signal)becomes extremely small. Since limit time determination circuit 16B usedin AD converter 10B includes a D latch circuit, a scan chain for a scantest can be readily configured.

Fourth Embodiment

FIG. 10 is a diagram showing the configuration of a part of an ADconverter according to the fourth embodiment. An AD converter 10Caccording to the fourth embodiment has a configuration obtained by morespecifically modifying limit time determination circuit 16 in FIG. 2.

Referring to FIG. 10, limit time determination circuit 16C includes: areplica comparator 34 having the same configuration as that ofcomparator 11; and a replica logic gate (NAND gate) 35 having the sameconfiguration as that of logic gate (NAND gate) 15. As with comparator11, replica comparator 34 is brought into a reset state (each of thepositive phase and the negative phase of the differential output signalattains an H level) when clock signal CLKCOMP is negated. Then, whenclock signal CLKCOMP is asserted, replica comparator 34 starts acomparison operation. The differential output signal of replicacomparator 34 is input into replica logic gate 35, and the output signalof replica logic gate 35 is input into logic gate (OR gate) 17 as outputsignal Sub_in of limit time determination circuit 16C.

An input potential difference 36 of replica comparator 34 is set at theminimum potential difference that comparator 11 must determine. Forexample, input potential difference 36 is set at a value that is 0.5times as that of LSB of the AD converter. Since the potential differencesmaller than this minimum potential difference (0.5 LSB) is smaller thana quantization error, and therefore, does not have to be distinguishedby comparator 11. When DA converter 14 includes a resistance ladder, 0.5LSB of input potential difference 36 can be readily extracted by furtherresistance-dividing one tap of the resistance ladder.

According to limit time determination circuit 16C of the above-describedconfiguration, the limit time period used as a reference as to whetherto proceed to the next cycle or not is determined in accordance withinput potential difference 36 of replica comparator 34 (for example, 0.5LSB). Specifically, when the absolute value of differential input signalDACOUT of comparator 11 is larger than input potential difference 36 ofreplica comparator 34 (0.5 LSB), the output of comparator 11 settlesbefore output signal Sub_in of limit time determination circuit 16C isasserted (that is, before the limit time period has passed). Incontrast, when the absolute value of differential input signal DACOUT ofcomparator 11 is smaller than input potential difference 36 of replicacomparator 34 (0.5 LSB), output signal Sub_in of limit timedetermination circuit 16C is asserted (that is, the limit time periodhas passed) before the output of comparator 11 settles.

Since other configurations of AD converter 10C are the same as those inFIG. 2, description thereof will not be repeated. In FIG. 10, the samecomponents as those in FIG. 2 are designated by the same referencecharacters.

According to AD converter 10C in the fourth embodiment described above,as in the first embodiment, an AD conversion value with a relativelysmall error can be obtained within a desired time period even when theabsolute value of the input potential difference of comparator 11 in acertain cycle (that is, the value of the differential input signal)becomes extremely small. Particularly, since the limit time period isdetermined in accordance with input potential difference 36 of replicacomparator 34, adjustment of the delay time of delay circuit 30 as inthe second and third embodiments is not required.

Fifth Embodiment

FIG. 11 is a diagram showing the configuration of a part of an ADconverter according to the fifth embodiment. An AD converter 10Daccording to the fifth embodiment is obtained by modifying AD converter10A in FIG. 6. Specifically, AD converter 10D in FIG. 11 is differentfrom AD converter 10A in FIG. 6 in that an exclusive-OR (EX-OR) gate 15Ais provided in place of NAND gate 15.

AD converter 10A in FIG. 6 poses a problem that, when a common voltageof differential output signal LATCHOUT of comparator 11 changes tothereby cause each of positive phase signal LATCHOUTP and negative phasesignal LATCHOUTN to attain an L level, output signal Main_in of logicgate (NAND gate) 15 is asserted, with the result that the VALID signalis to be asserted. On the other hand, according to an AD converter 10Din FIG. 11, even when the common voltage of differential output signalLATCHOUT of comparator 11 changes to thereby cause each of positivephase signal LATCHOUTP and negative phase signal LATCHOUTN to attain anL level, output signal Main_in of logic gate (EX-OR gate) 15A and theVALID signal are kept negated.

Since other configurations of AD converter 10D are the same as those inFIG. 6, description thereof will not be repeated. In FIG. 11, the samecomponents as those in FIG. 6 are designated by the same referencecharacters. Also in AD converters 10, 10B and 10C shown in FIGS. 2, 9and 10, respectively, an EX-OR gate can be employed in place of NANDgate 15.

Although the invention implemented by the present inventors have beenspecifically described based on the embodiments, it is obvious that thepresent invention is not limited to the above-described embodiments, butthe features thereof can be variously modified without departing fromthe scope of the invention.

REFERENCE SIGNS LIST

1 semiconductor device, 10, 10A, 10B, 10C, 10D AD converter, 11comparator, 12 SR latch circuit, 13 control circuit, 14 DA converter, 15logic gate (NAND gate), 15A logic gate (exclusive-OR gate), 16, 16A,16B, 16C limit time determination circuit, 17 OR gate, 18 clockgeneration circuit, 20 successive approximation control circuit, 29register, 30 delay circuit, 32 D latch circuit, 34 replica comparator,35 replica logic gate, CLKCOMP clock signal, TP1 limit time period, VIN(VINP, VINN) analog input signal, CC comparison code, Main_in outputsignal of NAND gate (EX-OR gate), Sub_in output signal of limit timedetermination circuit.

1. A successive approximation type AD (Analog-to-Digital) convertercomprising: a DA (Digital-to-Analog) converter that convert a comparisoncode; a comparator that compares an analog input signal and an outputsignal of said DA converter responding to a clock signal; and a controlcircuit, wherein said control circuit includes: a first determinationunit for outputting a first determination signal corresponding to anoutput of the comparator; a second determination unit for outputting asecond determination signal responding the clock signal; and a firstcontrol unit for updating said comparison code responding to said firstand second determination signals.
 2. The AD converter according to claim1, wherein said first determination unit outputs said firstdetermination signal asserted when the output of said comparatorsettles; said second determination unit generates said seconddetermination signal asserted when said limit time period has passedsince said comparator started the comparison operation; and said firstcontrol unit updates said comparison code when at least one of saidfirst and second determination signals is asserted.
 3. The AD converteraccording to claim 2, wherein said comparator starts the comparisonoperation when said clock signal is asserted, said control circuitfurther includes a second control unit for generating said clock signal,and said second control unit is configured to negate said clock signalin response to assertion of at least one of said first and seconddetermination signals, and to assert said clock signal when apredetermined time period has passed since said clock signal wasnegated.
 4. The AD converter according to claim 3, wherein said seconddetermination unit negates said second determination signal when saidclock signal is negated.
 5. The AD converter according to claim 4,wherein said second determination unit includes: a delay circuit fordelaying timing of each of rise and fall of said clock signal by saidlimit time period; and a first logic gate for generating said seconddetermination signal asserted when said clock signal is asserted and anoutput signal of said delay circuit is asserted.
 6. The AD converteraccording to claim 4, wherein said second determination unit includes: adelay circuit for delaying timing of each of rise and fall of said clocksignal by said limit time period; and a D latch circuit having: an inputterminal for receiving said clock signal; an inversion reset terminalfor receiving said clock signal; a clock terminal for receiving anoutput signal of said delay circuit; and an output terminal foroutputting said second determination signal.
 7. The AD converteraccording to claim 5, wherein a delay time of said delay circuit isadjustable in accordance with a set value of a register.
 8. The ADconverter according to claim 3, wherein said comparator is configuredto: output a comparison result by a differential signal formed of apositive phase signal and a negative phase signal; fix each of saidpositive phase signal and said negative phase signal to a first logiclevel when said clock signal is negated; and decide the output bychanging one of said positive phase signal and said negative phasesignal into a second logic level when said clock signal is asserted,said first determination unit includes a second logic gate forgenerating said first determination signal, and said second logic gateasserts said first determination signal when one of said positive phasesignal and said negative phase signal is at said first logic level andthe other of said positive phase signal and said negative phase signalis at said second logic level.
 9. The AD converter according to claim 8,wherein said second determination unit includes: a replica comparatorthat is identical in configuration to said comparator, and outputs, whena predetermined input voltage is input and said clock signal isasserted, a differential output signal according to the input voltage;and a replica logic gate that is identical in configuration to saidsecond logic gate, and generates said second determination signal basedon the differential output signal of said replica comparator, and saidlimit time period is determined in accordance with an input voltage ofsaid replica comparator.
 10. The AD converter according to claim 9,wherein the input voltage of said replica comparator is equal to onehalf of a voltage corresponding to a least significant bit of said ADconverter.
 11. The AD converter according to claim 8, wherein saidsecond logic gate includes an exclusive-OR gate.
 12. The AD converteraccording to claim 8, wherein said AD converter further includes an SRlatch circuit into which said positive phase signal and said negativephase signal from said comparator are input, an internal state of saidSR latch circuit does not change when each of said positive phase signaland said negative phase signal is at said first logic level, and changesinto a set state or a reset state in response to a change of one of saidpositive phase signal and said negative phase signal into said secondlogic level, and said first control unit generates said comparison code,based on an output signal of said SR latch circuit.
 13. The AD converteraccording to claim 6, wherein a delay time of said delay circuit isadjustable in accordance with a set value of a register.